Computer systems and data storage and transfer systems commonly employ random access digital memories (RAM) for storing input data information and permitting the reading out of that information at subsequent random times. In such memories, the address location of the data read into the memory and read from the memory generally is determined by digitally or binary encoded address leads comprising the outputs of a standard binary counter. High density memory systems generally employ MOS RAM memory chips which commonly are produced in standard capacities of 512 or 1024 bits.
In the manufacture of such memory chips, it is not uncommon for one or more bits or address locations in the chip to be faulty and incapable of reliably storing variable binary data. In addition, it is possible for chips which initially are not faulty to become faulty after installation into a system. This may occur either due to mishandling or to inherent weaknesses in the chip which result in a failure of one or more bit locations after prolonged usage.
Systems have been developed in the prior art for "prechecking" memory chips to determine whether or not particular address locations on such chips are bad or faulty. In most such systems, the faulty memory chips are used and the faulty sections are permanently bypassed to spare "replacement" memory chips of the same type into which input data is shunted in parallel with a supply of data to the main memory chip. Since the location of bad memory cells or address locations is done in advance, the shunting of information into the replacement memory is done under the control of permanently set gate circuits. If subsequent to installation into a memory system, a failure should take place in a memory cell in the main memory, such systems do not automatically divert data to be stored into the replacement memory; but such data is directed into the faulty memory. It is readily apparent that this can be highly inconvenient to a user of the system having such a memory in it, if not wholly catastrophic.
It is desirable to provide automatic monitoring and identification of faulty memory chips in a read/write memory system which prevents the entry of data into a faulty memory address location, and which further is capable of pinpointing the location of a faulty memory chip without requiring specific testing for faulty memory locations. Ideally, the identification of a faulty memory chip should be accomplished during normal operation of the system without disturbing that normal operation.